GSI TECHNOLOGY INC

GSI Technology, Inc.

Business model

• Fabless semiconductor company with two primary lines of business:
  • In-place associative computing (APU) products under the Gemini family and related platforms.
  • High-speed synchronous SRAM products for networking/telecom, test and measurement, military/defense, and aerospace markets.
• Commercialization approach for APU: proof-of-concept, pilot deployments, and targeted edge AI/HPC applications. SRAM operations continue to fund APU development.
• Headquarters in Sunnyvale, California, with operations in Taiwan and Israel. Wafer fabrication and assembly/testing are outsourced.

Products and services

• APU (associative processing unit) compute-in-memory products
  • Gemini family: Gemini I in full production; Gemini II in pre-production; ongoing development toward Plato.
  • Designed for low power, in-memory associative processing with short time-to-first-token (TTFT) for edge AI, multimodal vision-language workloads, and real-time processing.
  • Gemini II supports larger datasets, real-time inference, and 1-bit/ternary quantization workstreams to increase density and efficiency.
  • Board-level products: PCIe cards (Leda family: Leda-E2 full-size PCIe, Leda-S 1U form factor).
  • Software stack: APIs, libraries, compilers, and an integrated framework to accelerate compute-in-memory workloads.
• High-speed SRAM products (legacy business)
  • Four product families: SyncBurst, NBT, SigmaQuad, and SigmaDDR.
  • Densities up to 288 Mb with high random transaction rates; RadHard and RadTolerant variants for space and military use.
  • Master-die methodology to manufacture multiple product variations from a single mask set.
  • Radiation-hardened space-grade SRAMs and radiation-tolerant variants for avionics and space platforms.
  • Strong market position in high-performance memory for specific applications.
• Software and design services
  • APIs, libraries, toolchains, and IP (including FPGA controller IP) to support integration and development.

Markets and addressable market

• Target markets for APU: edge AI, high-performance computing, fast similarity/multimodal search, real-time SAR processing, cryptography, and large-scale vector search.
• TAM for APU (AI, search, HPC): approximately $247 billion in 2025, growing to about $708 billion by 2028.
• Serviceable available market (SAM) for edge AI deployments: roughly $7 billion in 2025, growing to about $16 billion by 2030.
• APU advantages: dynamic word-width flexibility, in-memory associative processing, multi-threaded workload handling, and reduced data movement latency and power.
• RadHard/RadTolerant SRAMs target military/defense and aerospace markets, including space applications.

Customers and channels

• Representative direct/end-user SRAM customers with purchases over $500k in fiscal 2026: BAE Systems, Cadence Design Systems, General Dynamics, IBM, KYEC, Nokia, Rockwell.
• Top customers by share of net revenues in SRAM:
  • KYEC: 14% (2026), 23% (2025), 3% (2024)
  • Nokia: 6% (2026), 12% (2025), 21% (2024)
  • Cadence Design Systems: 12% (2026), 8% (2025), 8% (2024)
• Channel and distributor reliance by fiscal year:
  • Avnet Logistics: 63.7% (2026), 49.6% (2025), 50.6% (2024)
  • Holystone: 14.2% (2026), 22.6% (2025), 2.5% (2024)
  • Nexcomm: 8.9% (2026), 9.8% (2025), 9.3% (2024)
  • Direct contract manufacturers: 4.9% (2026), 7.9% (2025), 20.5% (2024)
• Concentration risk: KYEC, Nokia, and Cadence have represented large portions of revenue; revenues can fluctuate quarter to quarter.
• Sales channels include direct, contract-manufacturer-based, and distributor-based models.

People, facilities, and intellectual property

• Employees: 125 full-time as of March 31, 2026.
  • Breakdown provided: 90 engineers (56 in R&D; 40 hold MS/PhD), 11 sales/marketing, 9 general and administrative, 49 manufacturing.
• Geographic distribution (as of 3/31/2026):
  • Sunnyvale, California: 38
  • Taiwan (Hsin Chu): 44
  • Israel: 36
• Intellectual property: 147 U.S. patents (59 memory patents; 88 associative computing patents); more than a dozen patent applications pending.

Revenue and profitability

• Fiscal 2026 net revenue grew 22% year over year versus fiscal 2025.
• APU revenue has been non-material to date; SRAM remains the primary revenue driver.
• Net losses: $13.2 million in 2026; $10.6 million in 2025; $20.1 million in 2024.
• Gross margin increased by 5 percentage points versus the prior fiscal year.
• Revenue mix and growth are influenced by SRAM demand, APU adoption, and SBIR-funded programs.

SBIR and government programs

• Four SBIR contracts related to APU compute-in-memory for military and space customers.
• Aggregate SBIR payments: approximately $557k in fiscal 2025 and $1.6 million in fiscal 2026.
• Notable awards and amounts:
  • Space Development Agency — Direct to Phase II (Prototype): $2.0 million (amended from $1.25 million).
  • AFRL — Direct to Phase II: $1.1 million.
  • U.S. Army SBIR Phase II: up to $250k.
  • U.S. Army xTech SBIR Phase II: $2.0 million.
• 2026 proof-of-concept engagements: Sentinel perimeter security program with G2 Tech (DoD and foreign government agency) announced January 2026.
• May 2026: Phase I Smart City project award in Taiwan (Gemini-II deployment).

Recent financing and capital actions

• October 21–22, 2025: Registered Direct Offering raised gross proceeds of approximately $50 million (shares at $10.00 and pre-funded warrants exercisable at $0.01).
• All pre-funded warrants were exercised in October 2025.

Manufacturing and operations

• Fabless model; wafers manufactured by TSMC (Taiwan) under purchase orders (no long-term supply contract).
• Process nodes:
  • APU wafers: 28 nm and 16 nm.
  • SRAM wafers: 0.13 µm, 90 nm, 65 nm, and 40 nm.
• Packaging handled by ASE (Taiwan); APU boards by Wistron Neweb (Taiwan).
• Radiation-hardened devices assembled and tested by Silicon Turnkey Solutions (Sunnyvale, CA).
• Two-phase manufacturing workflow:
  • Initial mask-set phase: ~13–15 weeks to generate multiple product possibilities.
  • Final processing, assembly, burn-in, test: ~8–10 weeks after order receipt.
• Supply risk: single-source wafers from TSMC and limited alternate sources; no long-term supplier contracts.

Intellectual property and regulatory

• Emphasis on IP protection via patents, confidentiality, and licensing; potential litigation risk in the IP space.
• Export control and dual-use considerations apply; government data rights from SBIR awards.
• Subject to insurance, cybersecurity governance, and regulatory compliance.

Strategic focus and outlook

• Transformation strategy: commercialize APU compute-in-memory products for AI and edge computing while maintaining and expanding the SRAM business.
• Plato (next-generation APU) aims to balance high compute with memory bandwidth, support external memory bandwidth upgrades, and enable 1-bit/ternary quantization for sub-20W edge applications.
• Gemini II targets extended TTFT capabilities and improved memory data locality for larger-model support.
• Market positioning depends on continued customer adoption, channel management, and execution of product milestones.

Key takeaways

• GSI operates two complementary businesses: legacy high-speed SRAM products that drive current revenue, and an APU compute-in-memory initiative (Gemini family, progressing toward Plato) intended as the growth engine.
• As of March 31, 2026, the company employed 125 people across Sunnyvale, Taiwan, and Israel, with a strong engineering focus.
• Fiscal 2026 revenue grew 22% year-over-year; net losses were $13.2 million in 2026, $10.6 million in 2025, and $20.1 million in 2024.
• The company depends on a few large customers and on a major distributor (Avnet Logistics). It also relies on a single primary wafer foundry (TSMC) without long-term contracts.
• Government SBIR funding supports APU R&D, with multiple awards and payments in 2025–2026.
• Gemini II and the Plato roadmap target low-power, low-latency edge AI across multiple workloads, with meaningful execution and commercialization risk.